The B-CAS BiDi Amplifier

Overview

When designing HF receivers or transceivers, it’s often desirable to have a gain block that can develop moderately high gain (>25 db)   with excellent 50 ohm input and output match, voltage adjustable gain, relatively high linear output drive capability, reasonably low noise figure and DC power economy. With the addition of a package of cheap C-MOS bus switches (a-la FST3257 or similar), this single amplifier could then be used as a bi-directional (BiDi) gain stage for both Rx and Tx in an economical transceiver design. This article describes a topology that I call the B-CAS amplifier (“Buffered HyCas”) which offers the above advantages, yet is built with a small number of common and low-cost components.

Background

In the April 2007 edition of QST, Hayward and Damm published a circuit topology known as the “Hybrid Cascode” or “HyCas”. (http://www.ka7exm.net/hycas/hycas_200712_qst.pdf).This circuit offers all the well-known benefits of an FET-input cascode amplifier with the added benefit of very wide voltage-controlled gain adjustment range.

Cascode amplifiers, and for that matter any amplifier based on the transconductance principle, are capable of very high voltage gain when the load impedance is also high. A problem for some applications is that the output stage must be matched, either via a transformer or a tuned LC network, into a 50 ohm load. However, the cascode amplifier structure is inherently limited in its output power capability by the current it can supply and the voltage swing available at the cascode output stage. If the matching network transforms the 50 ohm load into too low an impedance at the stage output, the stage becomes current limited. If the matching circuit transforms the load into too high an impedance, the stage becomes voltage-swing limited. In practice, the HyCas has a realizable power gain in the 15-20 dB range and a linear output power range up to about the milliwatt level. This is fine for receiver IF use, but for BiDi use in a transceiver, it would be nice to be able to deliver up to 10 mw or more, easing the gain requirements of the following exciter and power amplifier stages.

The B-CAS amplifier presented here adds a compound NPN/PNP output current driver stage to the HyCas amplifier, allowing the HyCas to deliver well over 30 dB of voltage gain into the high impedance driver input, while the driver can deliver the much higher current gain required to drive a 50 ohm load. The result is an amplifier that idles at around 18 ma total DC current, can easily deliver over 10 mw of linear output power, and has over 75 dB of voltage controlled gain adjustment range which can be used for Rx AGC and Tx ALC. The circuit has been thoroughly simulated and optimized in LTSpice and has been built for various frequencies from 6 mhz to 30 mhz. In principle, it should be usable to well over 50 mhz.

Description

The B-CAS amplifier is shown in the following schematic diagram.

Here are some design & construction notes:

1. This implementation is intentionally band-limited to prevent oscillation problems when used with C-MOS bus-switches in a BiDi configuration. If the gain of the amplifier were equal to or greater than the switch isolation at any frequency, the BiDi circuit would oscillate, Thus the effort to roll off high-frequency gain.

2. The amplifier is tuned to 9 mhz in this schematic, but can be retuned to other frequencies by adjusting the values of C1, L1, and L2. To tune the amplifier to 20 mhz, use the following values: L2 = 1.7u, C1 = 30p, L1 = 5u

1. The common-source JFET stage has an extremely high resistive component of its gate impedance.  At HF frequencies, it’s mostly capacitive. Therefore, matching the 50 ohm input is somewhat problematic. Simulations have shown that best noise figure is obtained when the input is matched to present a few thousand ohms to the gate. On the other hand, the losses of the input matching network will increase as the ratio of network Q to component Q increases. I chose to ‘fix’ the input impedance of the FET at 1000 ohms with a resistor (R13), yielding a matching network (L2 & C1) Q of about 4.5. With commonly available SMD inductors with Qs in the 30-50 range, this should limit network losses to 1db or better. The predicted noise figure is a little over 3db, not including matching network and switch losses. Input match is 30 db or better when the network is tuned properly.
2. The FET source bias resistor is shown at 91 ohms, but isn’t critical. I recommend 100 ohms as a nice round number.
3. L1 resonates the capacitance at the Q1/Q2 node. This resonance is very broad.
4. The idling bias current of the Q2/Q3 output driver stage has been set to about 13 ma, but can be adjusted by changing R6. At the present bias current, the amplifier’s 1db compression point is about +10dbm.
5. 10 db or more of additional overall gain is available by adjusting the gain swamping resistor at R2. It’s presently set for about 30 db, but simulations indicate over 40 db is available. I don’t recommend gains this high. This mod doesn’t extend the maximum output power available though.
6. Up to 6db more power gain and a correspondingly higher 1db compression level is available is available by reducing/eliminating resistors R1 & R4, at the expense of output match degradation. R1 & R4 are optimally 100 ohms for best match (30 db), but power loss goes up too. Reducing these too far will upset the bias and linearity though. I arbitrarily used 75 ohms for about 15 db of output match.

9. Gain control voltage at the base of Q1 should be about 4.5V (assuming an 8V supply) for maximum gain; minimum gain occurs somewhere around 0.5V. The gain control slope is very non-linear, as should be expected.

 

Shown below the schematic is the basic arrangement for turning the amplifier around from Rx to Tx. This can be done with relays or C-MOS bus switches such as the FST3257 and others. I have shown the latter.

The bus switches are powered from 5V. The output enable pin (OE) is grounded. The Select line (S) toggles the switches between Rx (low) and Tx (High). The resistors bias the bus switches to 2.5VDC so the RF signal is centered between Vcc and ground. There are 2 remaining switches in the package that could be used to switch other Rx/Tx analog functions such as audio, etc.

This has been proven to be a pretty solid circuit for me, though I’m still analyzing and optimizing.

 

 

Advertisement