Starting at the antenna, a Hybrid Cascode amplifier provides about 12 dB gain, very high isolation of the QSD from the antenna and about 70 dB of AGC range should be available, though the loop hasn’t been closed yet. The QSD is the well-known “Tayloe Detector” built with an FST3257 dual SPDT switch. The QSD is clocked by a quadrature clock generator built with a 74ACT74. This detector clock arrangement works well receiving up to at least 30 MHz. The I and Q outputs of the QSD are pre-amplified about 25 dB by 2 op-amps in a TL974 quad amplifier IC. The pre-amp outputs drive a 2-channel phase shift network. The PSN has 3 poles in each leg and is capable of about 45 dB opposite sideband rejection. The PSN outputs are lowpass and highpass filtered to set the receiver bandwidth of about 2.4 KHz. The filtered audio signal driver another section of TL974 with about 40 dB gain. This stage drives the AGC detector, which uses 2 sections of a TL974, as well as the speaker/headphones amplifier.
The local oscillator in the breadboard uses an Si5351 controlled by an Arduino, but an Si570 can also be used. Initial experiments confirm that the Si570 has much better phase jitter performance, especially receiving at the high end of the HF spectrum.
Initial performance testing indicates a sensitivity of better than 0.3uv for 10 dB signal-noise ratio at the output. Dynamic range, from MDS to visible distortion is at least 90 dB, limited only by the voltage swing of the op-amps that are powered by 5VDC. Sideband suppression is at least 40 dB, but no optimization hasn’t been done yet.
I’ll be working on this to close the AGC loop and to build a switched input bandpass filter. At that point, an all-band very high performance receiver will have been accomplished. Building a companion phasing-type SSB exciter would be the next logical step.
Stage-by-stage description:
The QSD demodulator
The audio phasing network
The audio processing stages
The audio power amplifier
I’ll publish more details as this design matures.
W3JDR Bright Ideas 